A conventional arrangement involving an analog-to-digital converter (hereinafter an “A/D converter”) is shown in FIG. 1, which shows a A/D converter 11 that converts an analog input signal into a digital value representative of the level of the input signal. In the arrangement shown in FIG. 1, the input signal is a differential signal, including a positive level signal 12 and a negative level signal 13. A/D converter 11 includes a corresponding pair of sampling capacitors 14 and 15 which are respectively connected for sampling of the input signal by controllable switches 16 and 17. The controllable switches are controlled by a signal PHS from switch controller 18.
In the arrangement shown in FIG. 1, input signals 12 and 13 are provided from the filtered output of low pass filter 19. Low pass filter 19 removes high frequency content such as content above the Nyquist sampling frequency of A/D converter 11, and also provides for gain control of sampled signal 20 which is designated here as “Vin”.
A timing diagram for control signal PHS, as output by switch controller 18, is shown in FIG. 2. As seen in FIG. 2, the conversion frequency of A/D converter 11 is 1/800 ns=1.25 MHz. Each cycle commences with a sampling cycle, which in this case is a 250 ns time period, in which the PHS signal is raised so as to close switches 16 and 17. The arrangement of switches while the PHS signal is high is shown in FIG. 1B. This permits sampling capacitors 14 and 15 to charge to a level corresponding to the input signal. After sampling capacitors 14 and 15 have charged to the level of the input signal, switch controller 18 lowers the PHS signal so as to open switches 16 and 17. Sampling capacitors 14 and 15 retain their sampled charges, and in the ensuing conversion period before a next sampling cycle begins, A/D converter 11 converts the sampled values into corresponding digital signals.
One drawback of the above conventional arrangement concerns reflection of a previously-sampled value back into the input of A/D converter 11. Consider a situation in which sampling capacitors 14 and 15 have been charged to levels VP2 and VN2 from a previous sampling cycle. After the previous sampling cycle ends, it is natural to expect that the input signals would continue to change, and this is shown in FIG. 1B which shows that the input signals have changed to a level of VP1 and VN1 at the beginning of the current sampling cycle. Thus, when switches 16 and 17 are closed so as to obtain a sample of the current input signal, there is a reflection of the voltage differential back into the input signal, which disturbs the value of the input signal away from its true value. Given the short sampling time (in this example, 250 ns), it is possible that the input signal might not settle to its true value before the sampling period is over. As a consequence, the values stored on sampling capacitors 14 and 15 will contain an error and will not accurately correspond to true values of the input signals.